CMOS Transition : Transition means changing from 0 to 1 or 1 to 0.
Raise time : The amount of time taken to change the transition from low voltage to high voltage ( usually 10% to 90% of VDD) is called Raise time .
OR The amount of time taken to charge the capacitor.
Fall Time : The amount of time taken to change the transition from high voltage to low voltage ( usually 90% to 10% of VDD) is called Fall time .
OR The amount of time taken to discharge the capacitor.
Load Capacitance (C-load) = Pin Capacitance (C-pin) + Net Capacitance (C-net)
Input Transition depends on the previous output transition in every cell.
Cell Delay : The time difference between 50% of the input transition to 50% of the output transition is called cell delay.
Cell delay depends on the output transition.
Parameter change in a cell due to load capacitance, Input Transition, mobility of electrons, supply voltage (VDD) and threshold voltage (Vth)
