What is Physical Design ?
Physical design refers to the process of converting a circuit high level logical description into its physical layout on a silicon chip.
Integrated Circuit : a compact semiconductor device that contains many interconnected electronic components, such as transistors and resistors, fabricated onto a single chip to perform various functions.
Foundry : related with fabricating of IC, foundry required GDS II file ( Graphic database system 2)
Design : means EDA (Electronic design automation) tool. It is a software tool. eg. synopsis, cadence, mentor graphics etc , knowledge of TCL scripting is required.
Design team will provide GDS II file to foundry for fabrication.
GDS II file consists of layout of cells and its connections. Connection of layout is called GDS.
Challenges for Design Engineer :
1) Complexity
2) Power Reduction
3) High speed operation
4) Area -lower Technologies (7nm, 4nm,3nm)
5) DRC :Design rule check for manufacturability should be implemented , it means following the rules for foundry.
Foundry examples : TSMC,Samsung foundry, Global Foundaries etc.
Power gating : cutting/disconnection of power is called Power Gating.
Clock Gating : cutting/disconnection of clock is called Clock Gating.
7nm(nanometer) : distance between source and drain of a transistor i.e. also known as channel length.
Mostly Physical Design Engineers will take care of DRC rules.
All the EDA tools are installed in LINUX O.S.
ASIC DESIGN FLOW - "Application Specific Integrated Circuit "
1) RTL Design : RTL - Register Transfer Logic"
These are the team where the RTL code is developed. Based on the functionality and behaviour of the circuit, these team designs the circuit which is written on VHDL or Verilog code.
2) DV : Design and Verification :
These are the team which will verify the functionality of the design (Design by RTL team) applying test case.
Usually system Verilog or UVM is used in DV.
3) Synthesis : It is the process of converting the RTL Code into Gate Level Netlist.
Inputs of Synthesis :
a) RTL code/netlist (.v or .VHDL)
b) Library Files/ Liberty Files (.lib) : .lib files consists of the information like area, power and timing information about standart cells.
Standart Cells : These are the simple cells which are already design and tested . Eg. INV (inverter), BUFF (buffer), OR, AND, NAND, NOR, XOR, MUX, DFF (D-flipflop), Latches etc.
SDC (Synopsis Design constraints ) : consists of clock information, I/P delay, Output Delay, Driving cell, PVT (process, Voltage & Temperature ) condition, RC corners (resistance & capacitance ), Set load etc.
example : defining a clock - create_clock -name mclk -period 1ns [get_ports clk ]
c) Output : Gate level Netlist (consists of Gate and its connections ).
Example : module temp (M,N,clk, rst,O );
input M,N,clk,rst;
Output O ;
wire n1, n2 ;
AND2X2 U1 (.A(M) , .B(N), .y(n1) ;
DFFARX1 U2 (.D(n1) , .CLK (clk) , .RST(rst), q(n2) , .qb(unconnected) );
INVX1 U3(.A(n2) , y(O) );
endmodule ();
4) DFT : Design for testability . DFT team will add some cells for testing but it will not affects the IC.
Testing IC after fabrication is called Post Silicon Validation. It is adding some layers in design to test IC after validation.
5) Physical Design : It will always starts with partition. The whole chip/IC is divided into various partition , each partition is known as block/tile.
Chiptop/SoC Engineer : means full chip Engineer
Each blocks may have more than 100K cells. Each block has a Core area (the area where all the standart cells and physical only objects are to be placed ) and a Die area (outer boundary of a block/chip) .
At the early stages in the career of Physical design Engineer, we are going to dealt in block level. After experience in block level, it is the full chip/ Soc level.
BLOCK LEVEL PHYSICAL DESIGN
1) Floorplanning : a) Creating core and Die area
b) Port Placement
c) Macro Placement
Macro : These are the complex cells which are already design and optimized. Generally Macro count will be ranges from 10 to 100.
d) Power Planning : Power Plan is required as every cells required VDD & VSS connections.
2) Placement : In this stage all the cells are placed inside the core area. Here we will analyze mainly focus on Congestion, Utilization, Max_ transition, Max_capacitance,Max_fanout & Setup Analysis.
3) STA (static timing analysis) : Here in this step we are going to analyze timing for different path in the design. We will analyze mainly on Setup & Hold, in-to-reg & reg-to-out, PVT Condition, Latency, skew, & Jitter, multicycle and Half cycle path etc. It is classified into two categories a) Pre layout STA ( from Synthesis to before routing ) b) Post Layout STA (after Routing )
4) Clock Tree Synthesis (CTS) : Here the clock tree is build using clock buffers and inverters. Clock tree is build to reduce the load in the clock pin. From this stage, the clock is going to propagate in the design.
5) Routing : Here in this step all the cells are physically connected with the metal layers.
6) Sign off Checks :
Primetime and StarRC tools : used for timing sign off.
IR Drop check : RedHawk