Input Files in Physical Design
The input in physical design can be classified into two categories : a) Design Related (design dependent )and b) Technology related (design independent)
Design Related :
1. Gate Level netlist (.v/.VHDL) 2. SDC (synopsis design constraint) (.sdc) 3. UPF (unified power format) (.upf) 4. Scandef (provided by DFT team after DV)
Technology Related :
1. Liberty file (.lib) 2. LEF (layout exchange format ) (.lef) 3. TF (technology file) (.tf) 4. tlu+ (table lookup )
Gate Level Netlist (.v) : Netlist will have standart cell and its connections . These netlist can be either in hierarchical or flat.
Hierarchical : Standart cells are present in top module and in sub modules.
Flat : all standar cells are present in the top module.
A gate level netlist has a cell instantiation. Cell Instantiation has 3 parts viz. Library cell name/ reference name, cell name/Instance name and Port Mapping.
Example : INVX1_RVT U1 (.A(s1) .Y(n1) ); where INVX1_RVT is the library cell name/reference name; U1 is the cell name/Instance name and (.A(s1) .Y(n1) ) is called port mapping.
Liberty file (.lib) : Format will be in the form of saed_32rvt_ss0p95v125c.lib
saed - Synopsys Armania Educational Department)
32 - 32nm Technology node
rvt - regular threshold voltage
ss - slow slow
95v - 0.95volt
p - point
125c - 125 degree Celsius
.db/.lib - .db is the compile form of .lib
The liberty file consists of the following information :
a) Wire Load Model
b) For each cell - 1. Area of a cell
2. Functionality of a cell
3. Input pin capacitance on all input pins.
4. Maximum transition limit on all input pins.
5. Max-transition and Max-capacitance limit on all output pins.
6. Leakage Power
7. Table of internal power (rise power & fall power)
8. Table of output transition
9. Table of cell delay.
Flavors of cell : HVT(high threshold voltage), RVT, LVT, ULVT etc.
Types of process : ss(slow slow - which means both pmos and nmos in a CMOS are both slow slow) , tt(typical typical), ff(fast fast)
Wire load Model : To estimate the R & C values before placement, we use WIRE LOAD MODEL. R & C values are calculated based on estimated net length. Net length is estimated based on fanout.
In WLM, Resistance on n1 net, Rn1 = L*RL ; L= net length, RL = resistance per unit length in micrometer
To calculate net delay we use : a) Elamore model b) Aurnoldi model (used in routing stage for more accuracy)
For pin : output transition is represented in rows and input transition will be represented in columns.
Extrapollation : If the values of transition is more than the table of contents, then the tools will calculate the value using mathematical calculation called extrapolation. Extrapollation is not accurate.
Technology file (.tf) : In cadence it is called tech-lef. This file consists of metal layer information and via rules. It also consists of site row information.
Via : Whenever there is any intersection of metal layers, via is formed. Via is required in order to connect any two metal layer.
Site row: Imaginary line provided by foundry, where the standart cells are going to put exactly above the site row. The width and height of standart cells should be the integer multiples of site row and site column.
The reason for putting a standart cell exactly in site row is it is easy for fabrication for keeping the N-well continuity.
The technology file also consists of metal density rules and current density rules.
Metal Density rules : metal density should be minimum of 40% to a maximum of 70% in a window. If the density doesn't meet, then dummy metal fill is used.
Current density rules : A metal layer given length and given width in which current can pass through it.
LEF (layout exchange format) : It consists of the abstract layout information of a cell. LEF view is also called as frame view.
For each cell, LEF consists the following information : 1. Width and height of a cell 2. Allowed orientation of a cell. 3. Layer of a pin 4. Co-ordinates of a pin 5. Other layer co-ordinates like N well & Polysilicon .
LEF is different for different flavour of cells.
Tlu+ file : Table lookup file . this is the compile version of ITF (Interconnect Technology Format) . Tlu+ file consists of R & C of metal layer per unit length for different width . It consists of parasitic R & C Information per micro meter.
This file is used after Placement stage. It consists of Cmax (more delay), for setup analysis and Cmin (less delay), for hold analysis.
SDC(synopsis design constraints ) : SDC is a common format for constraining the design which is supplied by all synthesis PnR and other tools. SDC file syntax is based on TCL format and all commands of SDC file follow the TCL syntax.
Constraints in the SDC file :
A. Header : It consists of SDC version and units of measurement of quantities like ns(nano seconds) for time, kohm for resistance , pF (pico farad) for capacitance etc.
example : set_units -time ns -resistance kohm -capacitance pF -voltage V -current mA
B. System Interface :
1. Set Driving Cells : Specifies the drive characteristics of Input or inout ports that are driven by the cells in the technology library.
eg. set_driving_cell -lib_cell IV [K5]
set_driving_load [lib_cell lib_cell_name ]
2. Set Load : This sets the load attribute on the specified ports and the nets in the current design.
eg. set_load -pin_load 0.005 [get_ports [port[11]]]
C. Design Rule Constraints : In this part basically maximum fanout, max & min Capacitance and max transition time are set.
1. Set maximum fanout : Maximum fanout load is set to a specify input port or design.
eg. set_max_fanout 5 [get_ports {port[10]}]
2. set_max_transition : Maximum transition time is set by this command.
eg: set_max_transition 2.5 [get_ports in]
D. Timing Constraints: In this part basically, we set clocks definitions, clk group, clk latency, clk uncertainity, clk transition, input delay, output delay, timing derates etc...
1. Create_clock: The create_clock command creates a clock object in the current design.
eg: create_clock -name "SYS_2X_CLK" -period 10 -waveform {0.0 5.0}
2. Create_generated_clock : It generates the clock object.
eg: create_generated_clock -multiply_by 2 -source CLK [get_pin <pin_name>]
3. Group_path : These are the set of paths or endpoints for the cost functions calculation. The group enable us to specify a set of paths to optimize even though there maybe a larger violations in the other groups.
eg: group_path -name "group1" -weight 2.0 -from {CLK1A} -to [get_ports FF1/D]
4. Clock_uncertainity : clock uncertainity adds some margin of error in to the system to account for variance in the clock network caused by non-ideality of clock network and clock source itself.
eg: set_clcok_uncertainity -setup 0.5 [get_clcoks CLK1]
set_clcok_uncertainity -hold 0.2 [get_clcoks CLK1]
5. Clock_latency : Clock latency specifies the amount of delay for a clock signal reaching to the clock pin of a sequential element from the clock source pin.
clock latency = network latency + source latency
Network latency = latency from clk definition point to clk pin of a register
Source latency = latency from PLL to the clock definition point in the design.
eg. set_clock_latency 2.55 [get_pins pin_name/Clk]
6. Input Delay : Input delay defines the time requirement of an input pin w.r.t clock edge. Inputs ports are assumed to have zero input delay if it is not specified.
eg. set_input_delay -max 1.22 -clock clk1 {ainput binput}
7. Output delay : Sets the output delay requirements on an output port.
eg. set_output_delay 1.8 -clock [get_clocks CLK2 ] [all_outputs ]
E. Timing Constraints :
1. Multicycle paths : This command specifies the number of cycles the data path must have for setup and hold check.
eg. set_multicycle_path 2 -from A -to B
2. False Path : A false path is a path that cannot propagate a signal.
For example, a path that is never activated by any combinations of inputs is a false path. False path should be disabled for timing analysis. Or a False path will be excluded for timing analysis.
eg. set_false_path -from U2/G -to U1/D