Parasitic Elements in VLSI Design
What are Parasitic Elements?
- Parasitic elements are unintended circuit elements that negatively affect chip performance.
- Also known as non-ideal elements, they result from physical limitations of fabrication.
Types of Parasitic Elements
- FEOL (Front-End of Line): Parasitics at the transistor level.
- MEOL (Middle-End of Line): Parasitics at the contact level (drain-to-source).
- BEOL (Back-End of Line): Parasitics in the interconnect layers (PnR level).
Parasitic Extraction (PEX)
PEX refers to extracting parasitic info like:
- Resistance (R)
- Capacitance (C)
- Inductance (L)
Data is extracted from the layout using EDA tools.
Parasitic File Formats
- DSPF (Detailed Standard Parasitic Format):
- Highly detailed info, useful for SPICE simulation.
- Captures every segment of a net.
- Large file size, high accuracy.
- RSPF (Reduced Standard Parasitic Format):
- Simplified version, faster analysis.
- Lower accuracy, better for large designs.
- SPEF (Standard Parasitic Exchange Format):
- Compact format of detailed parasitic data.
- Supports best, typical, and worst-case values.
- Commonly used in STA and IR analysis.
EDA Tools That Support SPEF
- Quantus – Cadence
- StarRC – Synopsys
- Calibre xACT 3D – Mentor/Siemens
SPEF File Structure
SPEF files have four main parts:
- Header Section: Includes design name, tool, naming styles, and units.
- Name Map Section: Shortens long net names.
Example:*509 F_C_EP2
*510 F_C_EP3
*511 F_C_EP4
- Port Section: Lists input/output/bidirectional ports.
Example:*PORTS
*1 I
*2 I
*3 O
*4 O - Parasitic Data Section: Each net has a
*D_NET
block.
Example:*D_NET regcontrol_top/GRC/n13345 1.94482 *CONN *I regcontrol_top/GRC/U9743:E I *C 537.855 9150.11 *L 3.70000 *I regcontrol_top/GRC/U9409:A O *C 540.735 9146.02 *D 5.40000 *CAP 1 regcontrol_top/GRC/U9743:E 0.936057 1 regcontrol_top/GRC/U9409:A regcontrol_top/GRC/U10716:Z 0.622675 *RES 1 regcontrol_top/GRC/U9743:E regcontrol_top/GRC/U9407:Z 10.7916 *END
Notes on Sections
- *CONN: Shows pin connections. Pins can be to instances (
*I
) or ports (*P
). - *CAP: Lists capacitance values – lumped or coupling.
- *RES: Lists resistance between nodes.